How the "Galaksija" Works in the First Few Microseconds
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Računari u vašoj kuči page 52-54
In any well-organized system, including the "Galaksija" computer, it is clear who issues commands, who is responsible for what, and who stands ready to "jump in to help" when called upon. You would be mistaken to think that the microprocessor is the "main boss." Although it is the largest, most complex, and consumes the most power on the entire computer board, it does nothing productive on its own—it merely executes commands issued by the ROM (EPROM 2732), or more precisely, the program written into it. However, even the ROM does not issue commands whenever it pleases but only when the microprocessor requests them. So, what actually happens in the "Galaksija" computer from the moment you turn it on?
Let’s say you’ve just turned on the computer. The transistor circuit T1, with resistors R4 and R5, electrolytic capacitor C6, and diode D1, keeps the microprocessor’s "RESET" pin at a low logic level (between 0 and 0.8V) for about half a second while C6 charges. Then, the transistor suddenly stops conducting, and the "pull-up" resistor RP raises the voltage on the same pin to a high logic level (above 2.4V), where it remains as long as the computer is running. This is the so-called initialization process, where the microprocessor is instructed to clear everything that might have been randomly stored in it at startup and begin its work anew.
The first thing it will do is ask the ROM for its first command. It does this practically as follows:
It sets each of the 16 address lines (A0 to A15) to a low logic level (i.e., the binary state is 0000 0000 0000 0000, which is address 0). It then pulls the MREQ (Memory Request) pin to a low logic level (the Z80A microprocessor uses negative logic, meaning a high logic level, represented by 1, is the "passive state," while a low level, represented by 0, is the "active state"). This calls the memory address 0. From the memory map, we see that this address belongs to the ROM. The only thing left is to specify whether this call represents a write to memory or a read from memory. Of course, since this is a request for a command, it’s a read operation, so the RD (read) pin will be active (low logic level). After all, one of the fundamental characteristics of ROM is that the microprocessor can only read from it, not write to it.
The 74LS156 decoder, which monitors the "high address lines" (A11 to A15) and thus roughly knows which part of the memory map is being called, activates output 0, which in turn activates the CE (Chip Enable) pin...
The ROM now knows it has been called upon and retrieves the required information from address lines A0 to A11, determining which of the total 4,096 bytes is being requested. It locates address 0 and places the data 1111 0011 (hexadecimal F3) on the 8-bit data bus.
The microprocessor reads the data &F3 from the bus, passes it to its internal instruction decoder, and learns that it has received the command DI (disable interrupt), meaning: "I will not allow anyone to interrupt my work—not even requests to generate a display on the screen. At least not until I receive the opposite command: EI (enable interrupt)."
Such a request will arrive soon. But since everything must proceed in order (unless an instruction demands an out-of-order action—the machine equivalent of a BASIC GOTO command), the microprocessor increments its program counter and reads the instruction at address 1. There, it finds the data 1001 0111 (or &97), which translates to SUB A, meaning: subtract the value of register A from itself and store the result in register A.
At first glance, what is the point of this seemingly absurd operation? Let’s see: no matter what value register A holds, after this operation, it will always be 0. So, is this simply a way to clear register A? Exactly!
And so on, meticulously and precisely, the microprocessor executes every command it receives from the ROM (or even from RAM, if you use the USR command). It jumps through memory, writes to RAM, and reads from it. Often, the program flow depends on which key you pressed, what program you loaded, or what signal arrived from the cassette tape—ultimately proving that even the ROM is not the "boss." You are, because the computer’s entire power is directed at executing every command you issue.
Making the Screen Work
Of course, it’s not enough for the computer to just run—its work must also be visible on the screen. To understand how the computer generates text or graphics, we must first grasp how a television displays an image.
The electron gun in a monochrome CRT (cathode-ray tube) constantly emits a thin beam of electrons toward the screen’s visible surface. Without deflection, this beam would only hit the center, leaving nothing but a bright dot. However, the deflection system uses precisely controlled magnetic fields to sweep the beam left-to-right, line by line, top-to-bottom, redrawing the entire image 50 times per second.
Since a uniformly lit screen carries no information, the CRT includes a control grid that regulates how many electrons reach the screen, thus determining brightness. A video signal modulates this grid: a higher positive voltage corresponds to a brighter spot, while a lower voltage produces darkness.
After each line is drawn (which happens 16,000 times per second on the "Galaksija," slightly deviating from the standard 15,625 Hz—a negligible difference), the computer sends a brief horizontal sync pulse—a signal "blacker than black," dropping the voltage even lower. When the last line finishes, a much longer vertical sync pulse follows. These negative pulses synchronize the TV’s (or monitor’s) deflection system with the video signal.
To display a full line of text, the electron beam must trace 13 horizontal lines, though only 9 are typically used for characters—the remaining 4 create spacing between rows.
The width of horizontal and vertical sync pulses is determined by RC circuits in the 74LS123 chip’s monostable multivibrators (with R12 and C3 controlling horizontal sync, and R13 and C4 handling vertical sync). These pulses are slightly longer than the standard specifies, as practice shows this yields a more stable image.
These two monostable multivibrators are triggered by the video divider chain, consisting of:
The 74LS93 counter (dividing the oscillator frequency by 15),
The CD4040 (dividing the first counter's output by 1024),
And the CD4017 (further dividing the resulting frequency by 10).
The final output frequency is:6,144,000 Hz ÷ 15 ÷ 1024 ÷ 10 = 50 Hz—the exact refresh rate at which the screen image is regenerated.
Interrupt Handling and Screen Generation
One output of the last chip in the video divider chain (CD4017) is fed—via an inverter (1/6 of the 74LS04 chip)—to the INT (interrupt) pin of the Z80A microprocessor. This means that every time this output activates (which happens whenever the electron beam is drawing the upper part of the screen, unless interrupts are disabled by the DI command), the microprocessor performs the following steps:
Acknowledges the interrupt request but does not halt until it finishes the current instruction (which can take up to 23 clock cycles).
Activates the M1 and IORQ pins, triggering a flip-flop (1/2 of the 74LS74 chip) and asserting its own WAIT (wait) pin.
Pauses execution while WAIT is active (low logic level), resuming only after the next horizontal sync pulse resets the flip-flop via its inverted output. This ensures perfect synchronization between the microprocessor and the screen refresh.
Saves its state: The return address (where it would have continued execution) and all register values are pushed to a dedicated memory location.
Jumps to the interrupt handler at address &0038 (a fixed location known only to the microprocessor’s designers) in the ROM.
Drawing the Screen
The microprocessor writes 0001 (binary) into the 74LS174 flip-flop, signaling the character generator (2716) to prepare the first line of the top text row.
It then reads the contents of video RAM addresses &2800–&281F (corresponding to the first text row).
Each byte (e.g., &5E for the letter "Š") is sent to the character generator, which outputs the pixel pattern for the current line (e.g., &AF for the top line of "Š"). This pattern is loaded into the 74LS164 shift register and clocked out at 6.144 MHz (each pixel lasts 0.00000016 seconds).
After drawing the line, the 74LS174 updates to 0010 (line 2), and the process repeats until all 13 lines of the row are rendered.
Once the entire screen is drawn, the microprocessor restores its saved state and executes RETN (return from interrupt), resuming normal operation as if nothing happened.
Keyboard Scanning
The keyboard uses a matrix layout (rows × columns) for efficiency. The 74LS156 decoder (note: the "Galaksija" has two of these chips) selects each row, while the 74LS251 selector detects column presses and relays them to the microprocessor’s D0 line.
When a key is pressed, the microprocessor verifies the signal 256 times to debounce it, then calculates the key’s position using:ROW × 8 + COLUMN.
While typing, the CPU spends 99% of its time scanning the keyboard—only briefly pausing to update video RAM before resuming scans.
Handling Commands
Special keys (BRK, DEL, LIST, or ENTER) trigger immediate actions:
ENTER:
The computer checks if the first character in the buffer is a digit (indicating a line number) or a letter (a direct command).
For line numbers, it converts the number to binary, searches memory for duplicates (deleting them if found), and inserts the new line into the program.
For commands (e.g., PRINT 5+5 or RUN), it executes them instantly by calling the relevant ROM routines.
Final Notes
If you’ve made it this far, you’re clearly someone who enjoys tackling logical challenges. Dive deeper into the literature—there are excellent books (and the "Galaksija" magazine’s regular columns) to guide you further!
Translated using:deepseek.
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